Sunday, March 30, 2008

Heathrow T5 Killed by Queueing

The British might seem to be alone right now when it comes to airport system fiascos, but the good ole USA is just as good, if not better, at mangling baggage systems. So, what happened? Well, of all the lame excuses, finger pointing and spin-doctoring for the media, this item caught my attention from a performance analysis perspective:

"But the underground conveyor system became clogged because staff failed to remove luggage quickly enough at the final unloading stage. So the system shut down. It's like a shopper putting too many goods on the supermarket check-out belt."

Because the baggage transfer area is tightly secured (we hope), there are no clandestine videos available from passenger cellphones. However, the following queue-theoretic simulation reveals what likely happened.

Click on the image to start the simulation.

Wednesday, March 26, 2008

Visualize This

Calling all those interested in improving the visualization of performance data (PerfViz). The following discussion group

Google Groups
Performance Visualization
Visit this group

has now been established. To join the group, just enter your email address and hit Subscribe.


Prospective authors interested in presenting a paper on PerfViz at CMG 2008, have until May 16th to submit an abstract and until June 13th to write a draft manuscript.

Building Perl PDQ with VisualStudio

PDQ user Alex Podelko reports a gotcha when building Perl PDQ with VisualStudio. His solution has been posted to the PDQ download page. Thanks, Alex!

Tuesday, March 25, 2008

Hickory, Dickory, Dock. The Mouse Just Sniffed at the Clock

Following the arrival of Penryn on schedule, Intel has now announced its "tock" phase (Nehalem) successor to the current 45 nm "tick" phase (Penryn). This is all about more cores (up to 8) and the return of 2-threads per core (SMT), not increasing clock speeds. That game does seem to be over, for example:

  • Tick: Penryn XE, Core 2 Extreme X9000 45 nm @ 2.8 GHz
  • Tock: Bloomfield, Nehalem micro-architecture 45 nm @ 3.0 GHz

Note that Sun is already shipping 8 cores × 8 threads = 64 VPUs @ 1.4 GHz in its UltraSPARC T2.

Nehalem also signals the replacement of Intel's aging frontside bus architecture by its new QuickPath chip-to-chip interconnect; the long overdue competitor to AMD’s HyperTransport bus. A 4-core Nehalem processor will have three DDR3 channels and four QPI links.

What about performance benchmarks besides those previously mentioned? I have no patience with bogus SPECxx_rate benchmarks which simply run multiple instances of a single-threaded benchmark. Customers should be demanding that vendors run the SPEC SDM to get a more reasonable assessment of scalability. The TPC-C benchmark results are perhaps a little more revealing. Here's a sample:

  • A HP Proliant DL380 G5 server 3.16GHz
    2 CPU × 4 cores × 1 threads/core = 8 VPU
    Pulled 273,666 tpmC on Oracle Enterprise Linux running Oracle 10g RDBMS (11/09/07)

  • HP ProLiant ML370G5 Intel X5460 3.16GHz
    2 CPU × 4 cores × 1 threads/core = 8 VPU
    Pulled 275,149 tpmC running SQL Server 2005 on Windows Server 2003 O/S (01/07/08)

  • IBM eServer xSeries 460 4P
    Intel Dual-Core Xeon Processor 7040 - 3.0 GHz
    2 CPU × 4 cores × 2 threads/core = 16 VPU
    Pulled 273,520 tpmC running DB2 on Windows Server 2003 O/S (05/01/06)

Roughly speaking, within this grouping, the 8-way Penryn TPC-C performance now matches a 16-way Xeon of 2 years ago. Note that the TPC-C Top Ten results, headed up by the HP Integrity Superdome-Itanium2/1.6GHz at 64 CPUs × 2 cores × 2 threads/core = 256 VPUs, are in the 1-4 million tpmC range.

The next step down is from 45 nm to 32 nm technology (code named Westmere), which was originally scheduled for 2013. Can't accuse Intel of not being aggressive.

Saturday, March 22, 2008

Corrigenda Available for GCaP Book

Looks like it's time to start a corrigenda page for my book, Guerrilla Capacity Planning: A Tactical Approach to Planning for Highly Scalable Applications and Services.

Special note added regarding J2EE/WebLogic listen threads in Chapter 7 and how they control application scalability.

You can submit an erratum online.

Wednesday, March 19, 2008

International Training at Bargain Prices

Google tells me that this blog has a lot of international readers. Additionally, I'm often asked if I plan to present my performance training classes at random locations around the world. Unfortunately, the logistics of doing that is much more difficult than is realized by the people who ask that question. But now, there is a solution! The U.S. dollar has fallen significantly against most other currencies, so it's cheaper for you to travel here, than for me (to charge you) to travel there. And who doesn't want to visit San Francisco? :-)

The U.S. dollar prices shown on the 2008 Training Schedule (PDF) can be converted to another currency using any of the following selection of multipliers:

    Australia ..... 1.08
    Brazil ........ 1.71
    Canada ........ 0.99
    China ......... 7.08
    Euro .......... 0.63
    India ......... 40.2
    Japan ......... 98.23
    Korea ......... 1008.4
    Malaysia ...... 3.15
    Switzerland ... 0.99
    Taiwan ........ 30.72
    Thailand ...... 31.1
    U.K. .......... 0.49

If your currency is not shown here, try this online currency converter. I look forward to seeing more international students in our classes this year.

Monday, March 17, 2008

USA High Tech R&D Trending Down

We've come a long way since Thomas Edison, baby! Among other things, the Wizard of Menlo Park (the one in Joizee, not California) also invented the concept of the modern industrial research lab; existing outside and independently of the cloisters of academia, where most significant research was done prior to Edison. So effective was Edison's Yankee ingenuity, that it was ultimately embraced by such emblematic American corporations as AT&T (Bell Labs), HP (Labs), IBM (Watson Labs), and Xerox (PARC), as well similar companies in Europe (Philips, Siemens) and, of course, Japan. In fact, 25 years ago, Japan had the USA so threatened by its growing economic clout that it would have been considered suicidal for the U.S. not to invest heavily in R&D.

Now, we read that U.S. high-tech R&D is trending downward even further; the PC language is "narrowing our focus" . Like the continual reduction in the Fed Prime Rate, how low can you go before you have no effect? Moreover, how can such trends have been considered suicidal 25 years ago but embraced today? Japan has not gone away, and now China and India also loom as respectable tech competitors in their own right. Not being an economist, I can only think of one explanation: Wall Street. Actually, it's not exactly a new trend because it began more subtly around 15-20 years when the aforementioned corporations slowly started to divest themselves of the large-budget Edison model. Why would they do that? It's around that same time that the U.S. population at large started becoming more invested in Wall St., either directly or indirectly (e.g., retirement accounts). This trend has since been adopted in places like Europe and Australia.

The Street demands short-term gains be reported quarterly, no matter how that goal is accomplished; witness the current sub-prime banking debacle as one potential outcome of trying to meet such insane demands. But if profits in the USA are up (as they measureably are--or have been until very recently), why is there less money going into R&D? Shouldn't the percentage of profits, at least, remain constant? To answer this question, I would point to none other than "Mr. Capitalism" himself, Warren E. Buffet (see if you can guess his point before clicking on the link). Just as the deregulated financial industry has imploded (again--lest we forget the S&L debacle of the late 80's), I think Edison would be appalled at the self-destructive shift of profits out of R&D and into executive compensation packages. Sadly, it seems the Wizard of Menlo Park continues to be overshadowed by the Wizards of Wall Street. OK, end of rant.

Saturday, March 8, 2008

Watch Your Knees and Queues

Beware of optical illusions!

The above plot, showing the normalized response times (R/S) for an M/M/m queue (i.e., a single waiting line with m servers), popped up several times at Hotsos 2008. The M/M/m queue can be employed to model the performance of multiple Oracle processes. Here, the curves correspond to m = 1 (black), 2, 3, 9, 16 (blue) plotted against average server utilization.

Friday, March 7, 2008

Hotsos 2008: Day 3

Only two things happened today; I gave my presentation on "Better Performance Management through Better Visualization Tools" and I met with Bob Sneed because he also asked my to review his presentation.

Hotsos 2008: Day 2

Tanel Poder continued his theme of better ways to collect Oracle performance data by demonstrating how his "Sesspack" (Oracle session level) data could be visualized using VBA calls to Excel charting functionality. He used Swingbench as a load generator for his demos. Afterwards, I spoke with him about my talk tomorrow and he said he was interested and would attend.